In recent years, to reduce the line width or the space width of a semiconductor device, a sidewall transfer method (hereinafter, also “double patterning method”) using sidewall spacers has been developed. For example, in a NAND flash memory, a plurality of word lines are often formed using the double patterning method to set the interval between adjacent ones of the word lines to be equal to or smaller than the minimum processing dimension of a lithography technique. In such a NAND flash memory, the width of spaces (hereinafter, also denoted by S0) between memory strings each constituted of a plurality of memory cells connected in series and select gate transistors for selecting the memory strings is also increasingly reduced to an interval substantially equal to the interval between adjacent ones of the word lines. This is to suppress gouging of a semiconductor substrate at the spaces S0 and to further downscale the semiconductor device. To reduce the width of the spaces S0 to be as narrow as the interval between the word lines and to downscale the semiconductor device, the sidewall spacers also need to be formed narrow.
However, when the sidewall spacers are narrow, it is difficult to align a photoresist with the sidewall spacers at memory string ends at a lithography step for forming gates of the select gate transistors. For example, an alignment accuracy of an ArF immersion exposure machine is about ±10 to 15 nanometers. In this case, when the width of the sidewall spacers is below about 20 nanometers, it is difficult to align the photoresist with the sidewall spacers. If the photoresist is misaligned with the sidewall spacers at the memory string ends, the select gate transistors may be electrically disconnected from the memory strings or gates of memory cells at the memory string ends are connected to the gates of the select gate transistors.